License checkout: synplifypro_asix

Starting:    C:\Programme\Synplicity\fpga_80\bin\mbin\synplify.exe
Version:     Synplify Pro 8.0, Build 189R
Date:        Tue Mar 29 20:44:26 2005
Build Type:38
Arguments:   -pro -batch -splash -launchmode top_level.prj -tcl top_level_map.tcl
ProductType: synplify_pro
License: synplifypro_asix node-locked
Running in Xilinx Mode



Running synthesis on top_level:fpga_config

log file: "c:\projekte\virtex_ii_xc2v250_board\cpld\fpga_config\top_level.srr"


Running Vhdl Compiler...

Job: "Vhdl Compiler" terminated with error status: 2.
See log file: "c:\projekte\virtex_ii_xc2v250_board\cpld\fpga_config\top_level.srr"


Vhdl Compiler exited with errors

Vhdl Compiler: 2 errors, 0 warnings, 1 note - from log file c:\projekte\virtex_ii_xc2v250_board\cpld\fpga_config\top_level.srr


Total: 2 errors, 0 warnings, 1 note

TCL script complete: "C:\projekte\Virtex_II_XC2V250_board\cpld\FPGA_Config\top_level_map.tcl"

exit status=2


#Program: Synplify Pro 8.0
#OS: Windows_NT

$ Start of Compile
#Tue Mar 29 20:44:27 2005

Synplicity VHDL Compiler, version 3.0.0, Build 286R, built Jan 13 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

VHDL syntax check successful!
File D:\projekte\Virtex_II_XC2V250_board\cpld\FPGA_Config\top_level.vhd changed - recompiling
@N:CD627 : top_level.vhd(11) | Synthesizing work.top_level.behavioral 
@E:CD392 : top_level.vhd(38) | Can't convert expression to type std_logic
@E:CD392 : top_level.vhd(38) | Can't convert expression to type std_logic
Synthesis failed
2 errors during synthesis
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime