License checkout: synplifypro_asix Starting: C:\Programme\Synplicity\fpga_80\bin\mbin\synplify.exe Version: Synplify Pro 8.0, Build 189R Date: Mon Mar 07 21:08:59 2005 Build Type:38 Arguments: -pro -batch -splash -launchmode top_level.prj -tcl top_level_map.tcl ProductType: synplify_pro License: synplifypro_asix node-locked Running in Xilinx Mode Running synthesis on top_level:usb_test log file: "c:\projekte\virtex_ii_xc2v250_board\fpga\usb_test\top_level.srr" Running Vhdl Compiler... Vhdl Compiler Completed Vhdl Compiler: 0 errors, 1 warning, 2 notes - from log file c:\projekte\virtex_ii_xc2v250_board\fpga\usb_test\top_level.srr Total: 0 errors, 1 warning, 2 notes Running VIRTEX2 Mapper... Launching mapper in pro mode using FSM Exploration result file: "c:\projekte\virtex_ii_xc2v250_board\fpga\usb_test\top_level_fsm.sdc" VIRTEX2 Mapper Completed with warnings VIRTEX2 Mapper: 0 errors, 2 warnings, 8 notes - from log file c:\projekte\virtex_ii_xc2v250_board\fpga\usb_test\top_level.srr Total: 0 errors, 3 warnings, 10 notes TCL script complete: "C:\projekte\Virtex_II_XC2V250_board\fpga\usb_test\top_level_map.tcl" exit status=0 #Program: Synplify Pro 8.0 #OS: Windows_NT $ Start of Compile #Mon Mar 07 21:08:59 2005 Synplicity VHDL Compiler, version 3.0.0, Build 286R, built Jan 13 2005 Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved VHDL syntax check successful! @N:CD627 : top_level.vhd(6) | Synthesizing work.top_level.behavioral @W:CD280 : top_level.vhd(23) | Unbound component string_mem mapped to black box @N:CD627 : top_level.vhd(23) | Synthesizing work.string_mem.syn_black_box Post processing for work.string_mem.syn_black_box Post processing for work.top_level.behavioral @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime ###########################################################[ Synplicity Xilinx Technology Mapper, version 8.0.0, Build 381R, built Jan 19 2005 Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved Reading constraint file: c:\projekte\virtex_ii_xc2v250_board\fpga\usb_test\top_level.sdc Reading constraint file: c:\projekte\virtex_ii_xc2v250_board\fpga\usb_test\top_level_fsm.sdc @N: : | Using encoding styles selected by FSM Explorer. Data created on Fri May 28 13:41:17 2004 Reading Xilinx I/O pad type table from file <C:\Programme\Synplicity\fpga_80\lib/xilinx/x_io_tbl.txt> @N: : top_level.vhd(66) | Found counter in view:work.top_level(behavioral) inst mem_address[8:0] Clock Buffers: Inserting Clock buffer for port clk, TNM=clk Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ Net buffering Report for view:work.top_level(behavioral): No nets needed buffering. @N:FX164 : | The option to pack flops in the IOB has not been specified @W:BN105 : | Cannot apply constraint syn_encoding to tast_pushed[0:3] Writing Analyst data base c:\projekte\virtex_ii_xc2v250_board\fpga\usb_test\top_level.srm @N: : | Set autoconstraint_io Writing EDIF Netlist and constraint files @N: : | Set autoconstraint_io @N: : | Set autoconstraint_io Found clock top_level|clk with period 1000.00ns @W:MT253 : top_level.vhd(51) | Blackbox string_mem is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) ##### START OF TIMING REPORT #####[ # Timing Report written on Mon Mar 07 21:09:06 2005 # Top view: top_level Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 0 Constraint File(s): c:\projekte\virtex_ii_xc2v250_board\fpga\usb_test\top_level.sdc c:\projekte\virtex_ii_xc2v250_board\fpga\usb_test\top_level_fsm.sdc @N:MT195 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT196 : | Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock.. Performance Summary ******************* Worst slack in design: 993.926 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------- top_level|clk 1.0 MHz 164.6 MHz 1000.000 6.074 993.926 inferred Inferred_clkgroup_0 System 1.0 MHz 195.5 MHz 1000.000 5.116 994.884 system default_clkgroup ======================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------- top_level|clk top_level|clk | 1000.000 993.926 | No paths - | No paths - | No paths - ====================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* Input Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ---------------------------------------------------------------------------------------- LOCKED NA NA NA NA NA button[0] top_level|clk (rising) 0.000 0.000 996.003 996.003 button[1] top_level|clk (rising) 0.000 0.000 996.049 996.049 button[2] top_level|clk (rising) 0.000 0.000 996.057 996.057 button[3] top_level|clk (rising) 0.000 0.000 996.057 996.057 clk NA NA NA NA NA usb_TXE_n top_level|clk (rising) 0.000 0.000 998.127 998.127 ======================================================================================== Output Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ------------------------------------------------------------------------------------------ usb_RD_n NA NA NA NA NA usb_SIWU NA NA NA NA NA usb_WR top_level|clk (rising) NA 5.117 1000.000 994.883 usb_data[0] System (rising) NA 5.116 1000.000 994.884 usb_data[1] System (rising) NA 5.116 1000.000 994.884 usb_data[2] System (rising) NA 5.116 1000.000 994.884 usb_data[3] System (rising) NA 5.116 1000.000 994.884 usb_data[4] System (rising) NA 5.116 1000.000 994.884 usb_data[5] System (rising) NA 5.116 1000.000 994.884 usb_data[6] System (rising) NA 5.116 1000.000 994.884 usb_data[7] System (rising) NA 5.116 1000.000 994.884 ========================================================================================== ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for top_level Mapping to part: xc2v250fg256-5 Cell usage: FDC 5 uses FDCE 10 uses GND 1 use MUXCY_L 8 uses VCC 1 use XORCY 9 uses string_mem 1 use LUT1 1 use LUT2 9 uses LUT3 8 uses LUT4 4 uses I/O primitives: 17 IBUF 6 uses OBUF 11 uses BUFGP 1 use I/O Register bits: 0 Register bits not including I/Os: 15 (0%) Global Clock Buffers: 1 of 16 (6%) Mapping Summary: Total LUTs: 22 (0%) Mapper successful! Process took 0h:0m:5s realtime, 0h:0m:5s cputime ###########################################################]